Conventionally, recessed channel transistors (RCAT: Recessed Channel Array Transistors) have been developed as field effect cell transistors for semiconductor memory devices. In a recessed channel transistor, for example, a strip-shaped semiconductor region having a recess in the central portion is used as an active region, a gate electrode is arranged in this recess with a gate dielectric film formed from an oxide film or the like interposed therebetween, and source/drain regions are provided in both side surface portions of the recess.
A recessed channel transistor having such a configuration has characteristics such that the channel length can be effectively kept long while keeping the footprint of the transistor small by engraving the channel. Consequently, the recessed channel transistor can suppress short channel effects.
However, the recessed channel transistor has a problem in that the leakage current between the drain region and the gate electrode when the transistor is off increases. Specifically, the recessed channel transistor has source/drain regions arranged in parallel with the gate electrode in a recess direction. Moreover, the gate electrode is manufactured by embedding it in a substrate and this structure is difficult to make such that only the oxide film between the source/drain regions and the gate electrode is thicker than other portions. Therefore, the contact area between the source/drain regions and the gate electrode is large compared with conventional planar transistors and the tunnel distance between the source/drain regions and the gate electrode is short, thus, the tunnel current between the drain region and the gate electrode becomes significant as the leakage current (off-leakage current) when the transistor is off.